Описание библиотеки микросхемы 5023ВС016 процессора "Спутник"
system.c
См. документацию.
1 
68 #include "system.h"
69 
74 void NVIC_EnableIRQ(IRQn_T IRQn, uint32_t vec)
75 {
76  switch (IRQn)
77  {
78  case Watchdog:
79  NVIC_MUX->INTR_MUX_CTRL_Watchdog = NUM_INTR_VECTOR(vec);
80  NVIC_MUX->INTR_MUX_CTRL_Watchdog |=(uint32_t)(1<<31);
81  break;
82  case Timer1:
83  NVIC_MUX->INTR_MUX_CTRL_Timer1 =NUM_INTR_VECTOR(vec);
84  NVIC_MUX->INTR_MUX_CTRL_Timer1 |=(uint32_t)(1<<31);
85  break;
86  case Timer2:
87  NVIC_MUX->INTR_MUX_CTRL_Timer2 =NUM_INTR_VECTOR(vec);
88  NVIC_MUX->INTR_MUX_CTRL_Timer2 |=(uint32_t)(1<<31);
89  break;
90  case Timer3:
91  NVIC_MUX->INTR_MUX_CTRL_Timer3 =NUM_INTR_VECTOR(vec);
92  NVIC_MUX->INTR_MUX_CTRL_Timer3 |=(uint32_t)(1<<31);
93  break;
94  case Timer4:
95  NVIC_MUX->INTR_MUX_CTRL_Timer4 =NUM_INTR_VECTOR(vec);
96  NVIC_MUX->INTR_MUX_CTRL_Timer4 |=(uint32_t)(1<<31);
97  break;
98  case GPIOA:
99  NVIC_MUX->INTR_MUX_CTRL_GPIOA =NUM_INTR_VECTOR(vec);
100  NVIC_MUX->INTR_MUX_CTRL_GPIOA |=(uint32_t)(1<<31);
101  break;
102  case GPIOB:
103  NVIC_MUX->INTR_MUX_CTRL_GPIOB =NUM_INTR_VECTOR(vec);
104  NVIC_MUX->INTR_MUX_CTRL_GPIOB |=(uint32_t)(1<<31);
105  break;
106  case GPIOC:
107  NVIC_MUX->INTR_MUX_CTRL_GPIOC =NUM_INTR_VECTOR(vec);
108  NVIC_MUX->INTR_MUX_CTRL_GPIOC |=(uint32_t)(1<<31);
109  break;
110  case GPIOD:
111  NVIC_MUX->INTR_MUX_CTRL_GPIOD =NUM_INTR_VECTOR(vec);
112  NVIC_MUX->INTR_MUX_CTRL_GPIOD |=(uint32_t)(1<<31);
113  break;
114  case GPIOE:
115  NVIC_MUX->INTR_MUX_CTRL_GPIOE =NUM_INTR_VECTOR(vec);
116  NVIC_MUX->INTR_MUX_CTRL_GPIOE |=(uint32_t)(1<<31);
117  break;
118  case GPIOF:
119  NVIC_MUX->INTR_MUX_CTRL_GPIOF =NUM_INTR_VECTOR(vec);
120  NVIC_MUX->INTR_MUX_CTRL_GPIOF |=(uint32_t)(1<<31);
121  break;
122  case GPIOG:
123  NVIC_MUX->INTR_MUX_CTRL_GPIOG =NUM_INTR_VECTOR(vec);
124  NVIC_MUX->INTR_MUX_CTRL_GPIOG |=(uint32_t)(1<<31);
125  break;
126  case GPIOH:
127  NVIC_MUX->INTR_MUX_CTRL_GPIOH =NUM_INTR_VECTOR(vec);
128  NVIC_MUX->INTR_MUX_CTRL_GPIOH |=(uint32_t)(1<<31);
129  break;
130  case GPIOI:
131  NVIC_MUX->INTR_MUX_CTRL_GPIOI =NUM_INTR_VECTOR(vec);
132  NVIC_MUX->INTR_MUX_CTRL_GPIOI |=(uint32_t)(1<<31);
133  break;
134  case UART_1:
135  NVIC_MUX->INTR_MUX_CTRL_UART1 =NUM_INTR_VECTOR(vec);
136  NVIC_MUX->INTR_MUX_CTRL_UART1 |=(uint32_t)(1<<31);
137  break;
138  case UART_2:
139  NVIC_MUX->INTR_MUX_CTRL_UART2 =NUM_INTR_VECTOR(vec);
140  NVIC_MUX->INTR_MUX_CTRL_UART2 |=(uint32_t)(1<<31);
141  break;
142  case UART_3:
143  NVIC_MUX->INTR_MUX_CTRL_UART3 =NUM_INTR_VECTOR(vec);
144  NVIC_MUX->INTR_MUX_CTRL_UART3 |=(uint32_t)(1<<31);
145  break;
146  case UART_4:
147  NVIC_MUX->INTR_MUX_CTRL_UART4 =NUM_INTR_VECTOR(vec);
148  NVIC_MUX->INTR_MUX_CTRL_UART4 |=(uint32_t)(1<<31);
149  break;
150  case UART_5:
151  NVIC_MUX->INTR_MUX_CTRL_UART5 =NUM_INTR_VECTOR(vec);
152  NVIC_MUX->INTR_MUX_CTRL_UART5 |=(uint32_t)(1<<31);
153  break;
154  case UART_6:
155  NVIC_MUX->INTR_MUX_CTRL_UART6 =NUM_INTR_VECTOR(vec);
156  NVIC_MUX->INTR_MUX_CTRL_UART6 |=(uint32_t)(1<<31);
157  break;
158  case SPI_1:
159  NVIC_MUX->INTR_MUX_CTRL_SPI1 =NUM_INTR_VECTOR(vec);
160  NVIC_MUX->INTR_MUX_CTRL_SPI1 |=(uint32_t)(1<<31);
161  break;
162  case SPI_2:
163  NVIC_MUX->INTR_MUX_CTRL_SPI2 =NUM_INTR_VECTOR(vec);
164  NVIC_MUX->INTR_MUX_CTRL_SPI2 |=(uint32_t)(1<<31);
165  break;
166  case Spacewire1:
167  NVIC_MUX->INTR_MUX_CTRL_SPACEWIRE1 &=~NUM_INTR_VECTOR(vec);
168  NVIC_MUX->INTR_MUX_CTRL_SPACEWIRE1 |=NUM_INTR_VECTOR(vec);
169  NVIC_MUX->INTR_MUX_CTRL_SPACEWIRE1 &=~INTR_SRC_ENABLE;
170  NVIC_MUX->INTR_MUX_CTRL_SPACEWIRE1 |=INTR_SRC_ENABLE;
171  break;
172  case Spacewire2:
173  NVIC_MUX->INTR_MUX_CTRL_SPACEWIRE2 &=~NUM_INTR_VECTOR(vec);
174  NVIC_MUX->INTR_MUX_CTRL_SPACEWIRE2 =NUM_INTR_VECTOR(vec);
175  NVIC_MUX->INTR_MUX_CTRL_SPACEWIRE2 &=~INTR_SRC_ENABLE;
176  NVIC_MUX->INTR_MUX_CTRL_SPACEWIRE2 |=INTR_SRC_ENABLE;
177  break;
178  case MKPD1_NUM:
179  NVIC_MUX->INTR_MUX_CTRL_MKPD1 =NUM_INTR_VECTOR(vec);
180  NVIC_MUX->INTR_MUX_CTRL_MKPD1 |=(uint32_t)(1<<31);
181  break;
182  case MKPD2_NUM:
183  NVIC_MUX->INTR_MUX_CTRL_MKPD2 =NUM_INTR_VECTOR(vec);
184  NVIC_MUX->INTR_MUX_CTRL_MKPD2|=(uint32_t)(1<<31);
185  break;
186  case MKPD3_NUM:
187  NVIC_MUX->INTR_MUX_CTRL_MKPD3 =NUM_INTR_VECTOR(vec);
188  NVIC_MUX->INTR_MUX_CTRL_MKPD3|=(uint32_t)(1<<31);
189  break;
190  case MKPD4_NUM:
191  NVIC_MUX->INTR_MUX_CTRL_MKPD4 =NUM_INTR_VECTOR(vec);
192  NVIC_MUX->INTR_MUX_CTRL_MKPD4|=(uint32_t)(1<<31);
193  break;
194  case TMTX_NUM:
195  NVIC_MUX->INTR_MUX_CTRL_TMTX =NUM_INTR_VECTOR(vec);
196  NVIC_MUX->INTR_MUX_CTRL_TMTX|=(uint32_t)(1<<31);
197  break;
198  case TCRX_NUM:
199  NVIC_MUX->INTR_MUX_CTRL_TCRX =NUM_INTR_VECTOR(vec);
200  NVIC_MUX->INTR_MUX_CTRL_TCRX|=(uint32_t)(1<<31);
201  break;
202  case I2C_NUM:
203  NVIC_MUX->INTR_MUX_CTRL_I2C =NUM_INTR_VECTOR(vec);
204  NVIC_MUX->INTR_MUX_CTRL_I2C|=(uint32_t)(1<<31);
205  break;
206  case CAN1_NUM:
207  NVIC_MUX->INTR_MUX_CTRL_CAN1 =NUM_INTR_VECTOR(vec);
208  NVIC_MUX->INTR_MUX_CTRL_CAN1|=(uint32_t)(1<<31);
209  break;
210  case CAN2_NUM:
211  NVIC_MUX->INTR_MUX_CTRL_CAN2 =NUM_INTR_VECTOR(vec);
212  NVIC_MUX->INTR_MUX_CTRL_CAN2|=(uint32_t)(1<<31);
213  break;
214  case EDAC:
215  NVIC_MUX->INTR_MUX_CTRL_EDAC =NUM_INTR_VECTOR(vec);
216  NVIC_MUX->INTR_MUX_CTRL_EDAC|=(uint32_t)(1<<31);
217  break;
218  case RES_Q_NUM:
219  NVIC_MUX->INTR_MUX_CTRL_RES_Q =NUM_INTR_VECTOR(vec);
220  NVIC_MUX->INTR_MUX_CTRL_RES_Q|=(uint32_t)(1<<31);
221  break;
222  case RESERVE_P1_NUM:
223  NVIC_MUX->INTR_MUX_CTRL_RES_P1 =NUM_INTR_VECTOR(vec);
224  NVIC_MUX->INTR_MUX_CTRL_RES_P1|=(uint32_t)(1<<31);
225  break;
226  case RESERVE_P2_NUM:
227  NVIC_MUX->INTR_MUX_CTRL_RES_P2 =NUM_INTR_VECTOR(vec);
228  NVIC_MUX->INTR_MUX_CTRL_RES_P2|=(uint32_t)(1<<31);
229  break;
230  case RESERVE_P3_NUM:
231  NVIC_MUX->INTR_MUX_CTRL_RES_P3 =NUM_INTR_VECTOR(vec);
232  NVIC_MUX->INTR_MUX_CTRL_RES_P3|=(uint32_t)(1<<31);
233  break;
234  case RESERVE_P4_NUM:
235  NVIC_MUX->INTR_MUX_CTRL_RES_P4 =NUM_INTR_VECTOR(vec);
236  NVIC_MUX->INTR_MUX_CTRL_RES_P4|=(uint32_t)(1<<31);
237  break;
238  case DMA_SPI_1_TX:
239  NVIC_MUX->INTR_MUX_CTRL_DMASPI1_TX =NUM_INTR_VECTOR(vec);
240  NVIC_MUX->INTR_MUX_CTRL_DMASPI1_TX|=(uint32_t)(1<<31);
241  break;
242  case DMA_SPI_1_RX:
243  NVIC_MUX->INTR_MUX_CTRL_DMASPI1_RX =NUM_INTR_VECTOR(vec);
244  NVIC_MUX->INTR_MUX_CTRL_DMASPI1_RX|=(uint32_t)(1<<31);
245  break;
246  case DMA_SPI_2_TX:
247  NVIC_MUX->INTR_MUX_CTRL_DMASPI2_TX =NUM_INTR_VECTOR(vec);
248  NVIC_MUX->INTR_MUX_CTRL_DMASPI2_TX|=(uint32_t)(1<<31);
249  break;
250  case DMA_SPI_2_RX:
251  NVIC_MUX->INTR_MUX_CTRL_DMASPI2_RX =NUM_INTR_VECTOR(vec);
252  NVIC_MUX->INTR_MUX_CTRL_DMASPI2_RX|=(uint32_t)(1<<31);
253  break;
254  case DMA_UART_1_TX:
255  NVIC_MUX->INTR_MUX_CTRL_DMAUART1_TX =NUM_INTR_VECTOR(vec);
256  NVIC_MUX->INTR_MUX_CTRL_DMAUART1_TX|=(uint32_t)(1<<31);
257  break;
258  case DMA_UART_1_RX:
259  NVIC_MUX->INTR_MUX_CTRL_DMAUART1_RX =NUM_INTR_VECTOR(vec);
260  NVIC_MUX->INTR_MUX_CTRL_DMAUART1_RX|=(uint32_t)(1<<31);
261  break;
262  case DMA_UART_2_TX:
263  NVIC_MUX->INTR_MUX_CTRL_DMAUART2_TX =NUM_INTR_VECTOR(vec);
264  NVIC_MUX->INTR_MUX_CTRL_DMAUART2_TX|=(uint32_t)(1<<31);
265  break;
266  case DMA_UART_2_RX:
267  NVIC_MUX->INTR_MUX_CTRL_DMAUART2_RX =NUM_INTR_VECTOR(vec);
268  NVIC_MUX->INTR_MUX_CTRL_DMAUART2_RX|=(uint32_t)(1<<31);
269  break;
270  case DMA_UART_3_TX:
271  NVIC_MUX->INTR_MUX_CTRL_DMAUART3_TX =NUM_INTR_VECTOR(vec);
272  NVIC_MUX->INTR_MUX_CTRL_DMAUART3_TX|=(uint32_t)(1<<31);
273  break;
274  case DMA_UART_3_RX:
275  NVIC_MUX->INTR_MUX_CTRL_DMAUART3_RX =NUM_INTR_VECTOR(vec);
276  NVIC_MUX->INTR_MUX_CTRL_DMAUART3_RX|=(uint32_t)(1<<31);
277  break;
278  case DMA_UART_4_TX:
279  NVIC_MUX->INTR_MUX_CTRL_DMAUART4_TX =NUM_INTR_VECTOR(vec);
280  NVIC_MUX->INTR_MUX_CTRL_DMAUART4_TX|=(uint32_t)(1<<31);
281  break;
282  case DMA_UART_4_RX:
283  NVIC_MUX->INTR_MUX_CTRL_DMAUART4_RX =NUM_INTR_VECTOR(vec);
284  NVIC_MUX->INTR_MUX_CTRL_DMAUART4_RX|=(uint32_t)(1<<31);
285  break;
286  case DMA_UART_5_TX:
287  NVIC_MUX->INTR_MUX_CTRL_DMAUART5_TX =NUM_INTR_VECTOR(vec);
288  NVIC_MUX->INTR_MUX_CTRL_DMAUART5_TX|=(uint32_t)(1<<31);
289  break;
290  case DMA_UART_5_RX:
291  NVIC_MUX->INTR_MUX_CTRL_DMAUART5_RX =NUM_INTR_VECTOR(vec);
292  NVIC_MUX->INTR_MUX_CTRL_DMAUART5_RX|=(uint32_t)(1<<31);
293  break;
294  case DMA_UART_6_TX:
295  NVIC_MUX->INTR_MUX_CTRL_DMAUART6_TX =NUM_INTR_VECTOR(vec);
296  NVIC_MUX->INTR_MUX_CTRL_DMAUART6_TX|=(uint32_t)(1<<31);
297  break;
298  case DMA_UART_6_RX:
299  NVIC_MUX->INTR_MUX_CTRL_DMAUART6_RX =NUM_INTR_VECTOR(vec);
300  NVIC_MUX->INTR_MUX_CTRL_DMAUART6_RX|=(uint32_t)(1<<31);
301  break;
302  }
303  NVIC_En_IRQ(vec); /*< Разрешение прерываний*/
304 }
310 {
311  CMN_REG->PWR_CTRL_RST &= ~((uint32_t)(1 << CTRLn));
312 }
313 
319 {
320  CMN_REG->PWR_CTRL_RST &= ~((uint32_t)(1 << CTRLn));
321  CMN_REG->PWR_CTRL_RST |= (uint32_t)(1 << CTRLn);
322 }
323 
329 {
330  CMN_REG->PWR_CTRL_CLK &= ~((uint32_t)(1 << CTRLn));
331 }
332 
338 {
339  CMN_REG->PWR_CTRL_CLK &= ~((uint32_t)(1 << CTRLn));
340  CMN_REG->PWR_CTRL_CLK |= (uint32_t)(1 << CTRLn);
341 }
342 
347 void NVIC_DisableIRQ(uint32_t vec)
348 {
349  NVIC_Dis_IRQ(vec);
350 }
351 
352 void SystemInit (void)
353 {
355  CMN_REG->EDAC_CTRL |= EDAC_En_1 ;
356  CMN_REG->EDAC_CTRL |= EDAC_En_2 ;
357 }
358 
Definition: system.h:149
Definition: system.h:144
#define EXT_MEM_READ_CYCLES(x)
Макросы для регистра EXTMEM_CTRL.
Definition: system.h:235
#define NVIC_Dis_IRQ(X)
X - вектор прерывания
Definition: system.h:574
Definition: system.h:146
Definition: system.h:145
Definition: system.h:138
Definition: system.h:142
CTRL_T
Номера модулей в регистрах PWR_CLK_CTRL и PWR_RST_CTRL Расшифровка битовых полей для регистров PWR_CT...
Definition: system.h:635
Definition: system.h:139
void NVIC_EnableIRQ(IRQn_T IRQn, uint32_t vec)
Разрешение прерывания
Definition: system.c:74
void SystemInit(void)
Инициализация микросхемы
Definition: system.c:352
Definition: system.h:133
Definition: system.h:143
Definition: system.h:131
Definition: system.h:135
Definition: system.h:129
Definition: system.h:130
void PWR_CLK_Disable(CTRL_T CTRLn)
Отключение тактового сигнала от модуля
Definition: system.c:328
void PWR_RST_Disable(CTRL_T CTRLn)
Вывод модуля из асинхронного сброса
Definition: system.c:318
Definition: system.h:147
void PWR_CLK_Enable(CTRL_T CTRLn)
Подача тактового сигнала на модуль
Definition: system.c:337
Definition: system.h:141
Definition: system.h:161
#define NUM_INTR_VECTOR(x)
Definition: system.h:121
Definition: system.h:134
void NVIC_DisableIRQ(uint32_t vec)
Запрещение прерывания
Definition: system.c:347
#define NVIC_MUX
Указатель на структуру NVIC_MUX.
Definition: system.h:136
void PWR_RST_Enable(CTRL_T CTRLn)
Ввод модуля в асинхронный сброс
Definition: system.c:309
Definition: system.h:148
Definition: system.h:140
#define EXT_MEM_WRITE_CYCLES(x)
Definition: system.h:236
Этот файл содержит структуры, макросы и функции необходимые для взаимодействия с регистрами общего на...
IRQn_T
Номера прерываний в регистрах NVIC.
Definition: system.h:126
#define EDAC_En_1
Макросы для регистра EDAC_CTRL.
Definition: system.h:256
#define INTR_SRC_ENABLE
Макросы для INTR_MUX_CTRL.
Definition: system.h:120
Definition: system.h:132
#define EXT_MEM_TURN_CYCLES(x)
Definition: system.h:237
#define CMN_REG
Указатель на структуру CMN_REG.
#define NVIC_En_IRQ(X)
X - вектор прерывания
Definition: system.h:573
#define EDAC_En_2
Definition: system.h:257
Definition: system.h:137