80 NVIC_MUX->INTR_MUX_CTRL_Watchdog |=(uint32_t)(1<<31);
84 NVIC_MUX->INTR_MUX_CTRL_Timer1 |=(uint32_t)(1<<31);
88 NVIC_MUX->INTR_MUX_CTRL_Timer2 |=(uint32_t)(1<<31);
92 NVIC_MUX->INTR_MUX_CTRL_Timer3 |=(uint32_t)(1<<31);
96 NVIC_MUX->INTR_MUX_CTRL_Timer4 |=(uint32_t)(1<<31);
100 NVIC_MUX->INTR_MUX_CTRL_GPIOA |=(uint32_t)(1<<31);
104 NVIC_MUX->INTR_MUX_CTRL_GPIOB |=(uint32_t)(1<<31);
108 NVIC_MUX->INTR_MUX_CTRL_GPIOC |=(uint32_t)(1<<31);
112 NVIC_MUX->INTR_MUX_CTRL_GPIOD |=(uint32_t)(1<<31);
116 NVIC_MUX->INTR_MUX_CTRL_GPIOE |=(uint32_t)(1<<31);
120 NVIC_MUX->INTR_MUX_CTRL_GPIOF |=(uint32_t)(1<<31);
124 NVIC_MUX->INTR_MUX_CTRL_GPIOG |=(uint32_t)(1<<31);
128 NVIC_MUX->INTR_MUX_CTRL_GPIOH |=(uint32_t)(1<<31);
132 NVIC_MUX->INTR_MUX_CTRL_GPIOI |=(uint32_t)(1<<31);
136 NVIC_MUX->INTR_MUX_CTRL_UART1 |=(uint32_t)(1<<31);
140 NVIC_MUX->INTR_MUX_CTRL_UART2 |=(uint32_t)(1<<31);
144 NVIC_MUX->INTR_MUX_CTRL_UART3 |=(uint32_t)(1<<31);
148 NVIC_MUX->INTR_MUX_CTRL_UART4 |=(uint32_t)(1<<31);
152 NVIC_MUX->INTR_MUX_CTRL_UART5 |=(uint32_t)(1<<31);
156 NVIC_MUX->INTR_MUX_CTRL_UART6 |=(uint32_t)(1<<31);
160 NVIC_MUX->INTR_MUX_CTRL_SPI1 |=(uint32_t)(1<<31);
164 NVIC_MUX->INTR_MUX_CTRL_SPI2 |=(uint32_t)(1<<31);
180 NVIC_MUX->INTR_MUX_CTRL_MKPD1 |=(uint32_t)(1<<31);
184 NVIC_MUX->INTR_MUX_CTRL_MKPD2|=(uint32_t)(1<<31);
188 NVIC_MUX->INTR_MUX_CTRL_MKPD3|=(uint32_t)(1<<31);
192 NVIC_MUX->INTR_MUX_CTRL_MKPD4|=(uint32_t)(1<<31);
196 NVIC_MUX->INTR_MUX_CTRL_TMTX|=(uint32_t)(1<<31);
200 NVIC_MUX->INTR_MUX_CTRL_TCRX|=(uint32_t)(1<<31);
204 NVIC_MUX->INTR_MUX_CTRL_I2C|=(uint32_t)(1<<31);
208 NVIC_MUX->INTR_MUX_CTRL_CAN1|=(uint32_t)(1<<31);
212 NVIC_MUX->INTR_MUX_CTRL_CAN2|=(uint32_t)(1<<31);
216 NVIC_MUX->INTR_MUX_CTRL_EDAC|=(uint32_t)(1<<31);
220 NVIC_MUX->INTR_MUX_CTRL_RES_Q|=(uint32_t)(1<<31);
224 NVIC_MUX->INTR_MUX_CTRL_RES_P1|=(uint32_t)(1<<31);
228 NVIC_MUX->INTR_MUX_CTRL_RES_P2|=(uint32_t)(1<<31);
232 NVIC_MUX->INTR_MUX_CTRL_RES_P3|=(uint32_t)(1<<31);
236 NVIC_MUX->INTR_MUX_CTRL_RES_P4|=(uint32_t)(1<<31);
240 NVIC_MUX->INTR_MUX_CTRL_DMASPI1_TX|=(uint32_t)(1<<31);
244 NVIC_MUX->INTR_MUX_CTRL_DMASPI1_RX|=(uint32_t)(1<<31);
248 NVIC_MUX->INTR_MUX_CTRL_DMASPI2_TX|=(uint32_t)(1<<31);
252 NVIC_MUX->INTR_MUX_CTRL_DMASPI2_RX|=(uint32_t)(1<<31);
256 NVIC_MUX->INTR_MUX_CTRL_DMAUART1_TX|=(uint32_t)(1<<31);
260 NVIC_MUX->INTR_MUX_CTRL_DMAUART1_RX|=(uint32_t)(1<<31);
264 NVIC_MUX->INTR_MUX_CTRL_DMAUART2_TX|=(uint32_t)(1<<31);
268 NVIC_MUX->INTR_MUX_CTRL_DMAUART2_RX|=(uint32_t)(1<<31);
272 NVIC_MUX->INTR_MUX_CTRL_DMAUART3_TX|=(uint32_t)(1<<31);
276 NVIC_MUX->INTR_MUX_CTRL_DMAUART3_RX|=(uint32_t)(1<<31);
280 NVIC_MUX->INTR_MUX_CTRL_DMAUART4_TX|=(uint32_t)(1<<31);
284 NVIC_MUX->INTR_MUX_CTRL_DMAUART4_RX|=(uint32_t)(1<<31);
288 NVIC_MUX->INTR_MUX_CTRL_DMAUART5_TX|=(uint32_t)(1<<31);
292 NVIC_MUX->INTR_MUX_CTRL_DMAUART5_RX|=(uint32_t)(1<<31);
296 NVIC_MUX->INTR_MUX_CTRL_DMAUART6_TX|=(uint32_t)(1<<31);
300 NVIC_MUX->INTR_MUX_CTRL_DMAUART6_RX|=(uint32_t)(1<<31);
311 CMN_REG->PWR_CTRL_RST &= ~((uint32_t)(1 << CTRLn));
320 CMN_REG->PWR_CTRL_RST &= ~((uint32_t)(1 << CTRLn));
321 CMN_REG->PWR_CTRL_RST |= (uint32_t)(1 << CTRLn);
330 CMN_REG->PWR_CTRL_CLK &= ~((uint32_t)(1 << CTRLn));
339 CMN_REG->PWR_CTRL_CLK &= ~((uint32_t)(1 << CTRLn));
340 CMN_REG->PWR_CTRL_CLK |= (uint32_t)(1 << CTRLn);
#define EXT_MEM_READ_CYCLES(x)
Макросы для регистра EXTMEM_CTRL.
#define NVIC_Dis_IRQ(X)
X - вектор прерывания
CTRL_T
Номера модулей в регистрах PWR_CLK_CTRL и PWR_RST_CTRL Расшифровка битовых полей для регистров PWR_CT...
void NVIC_EnableIRQ(IRQn_T IRQn, uint32_t vec)
Разрешение прерывания
void SystemInit(void)
Инициализация микросхемы
void PWR_CLK_Disable(CTRL_T CTRLn)
Отключение тактового сигнала от модуля
void PWR_RST_Disable(CTRL_T CTRLn)
Вывод модуля из асинхронного сброса
void PWR_CLK_Enable(CTRL_T CTRLn)
Подача тактового сигнала на модуль
#define NUM_INTR_VECTOR(x)
void NVIC_DisableIRQ(uint32_t vec)
Запрещение прерывания
#define NVIC_MUX
Указатель на структуру NVIC_MUX.
void PWR_RST_Enable(CTRL_T CTRLn)
Ввод модуля в асинхронный сброс
#define EXT_MEM_WRITE_CYCLES(x)
Этот файл содержит структуры, макросы и функции необходимые для взаимодействия с регистрами общего на...
IRQn_T
Номера прерываний в регистрах NVIC.
#define EDAC_En_1
Макросы для регистра EDAC_CTRL.
#define INTR_SRC_ENABLE
Макросы для INTR_MUX_CTRL.
#define EXT_MEM_TURN_CYCLES(x)
#define CMN_REG
Указатель на структуру CMN_REG.
#define NVIC_En_IRQ(X)
X - вектор прерывания