Описание библиотеки микросхемы 5023ВС016 процессора "Спутник"
system.h
См. документацию.
1 
29 #ifndef SYSTEM_H_
30 #define SYSTEM_H_
31 
32 #include "chip_5023BC016.h"
33 #include "types.h"
34 
35 
36 
37 extern const uint32_t sys_freq;
38 extern const uint32_t spw_freq;
39 
40 #define CLK_INIT_PAUSE for(int i=0; i<100000; i++)
41 #define CLK_FPU_PAUSE for(int i=0; i<100; i++)
42 #define CLK_UART_PAUSE for(int i=0; i<10000; i++)
43 
47 typedef struct
48 {
54  __RW uint32_t RESERVED[3];
64  __RW uint32_t RESERVED1[7];
71  __RW uint32_t RESERVED2[2];
74  __RW uint32_t RESERVED3[2];
77  __RW uint32_t RESERVED4[2];
82  __RW uint32_t RESERVED5[4];
86  __RW uint32_t RESERVED6[1];
89  __RW uint32_t RESERVED7[2];
91  __RW uint32_t RESERVED8[3];
93  __RW uint32_t RESERVED9[3];
98  __RW uint32_t RESERVED10[28];
116 
120 #define INTR_SRC_ENABLE ((uint32_t)(1<<31))
121 #define NUM_INTR_VECTOR(x) ((uint32_t)((x&0x1F)<<0))
126 typedef enum
127 {
128  Watchdog = 0,
129  Timer1 = 1,
130  Timer2 = 2,
131  Timer3 = 3,
132  Timer4 = 4,
133  GPIOA = 8,
134  GPIOB = 9,
135  GPIOC = 10,
136  GPIOD = 11,
137  GPIOE = 12,
138  GPIOF = 13,
139  GPIOG = 14,
140  GPIOH = 15,
141  GPIOI = 16,
142  UART_1 = 24,
143  UART_2 = 25,
144  UART_3 = 26,
145  UART_4 = 27,
146  UART_5 = 28,
147  UART_6 = 29,
148  SPI_1 = 32,
149  SPI_2 = 33,
150  Spacewire1 = 36,
151  Spacewire2 = 37,
152  MKPD1_NUM = 40,
153  MKPD2_NUM = 41,
154  MKPD3_NUM = 42,
155  MKPD4_NUM = 43,
156  TMTX_NUM = 48,
157  TCRX_NUM = 49,
158  I2C_NUM = 50,
159  CAN1_NUM = 52,
160  CAN2_NUM = 53,
161  EDAC = 56,
162  RES_Q_NUM = 60,
183 } IRQn_T;
184 
187 typedef struct
188 {
189  __RW uint32_t EXTMEM_CTRL;
190  __RW uint32_t EDAC_CTRL;
195  uint32_t RESERVED;
199  __RW uint32_t PWR_CTRL_CLK;
200  __RW uint32_t PWR_CTRL_RST;
201  __RW uint32_t EXTMEM2_CTRL;
202  __RW uint32_t EXTMEM3_CTRL;
203  __RW uint32_t EXTMEM4_CTRL;
217  __RW uint32_t DMA_INTR_FLAGS;
218  __RW uint32_t ALT_FUNCTION_CTRL[9];
219  __RW uint32_t RESERVED_1[2];
223  __RW uint32_t ALIAS_CTRL;
227  __RW uint32_t GLOBAL_RESET;
228  __RW uint32_t RES_P_SYNC;
229  __RW uint32_t CACHE_MAIN;
230 }CMN_REG_T;
231 
235 #define EXT_MEM_READ_CYCLES(x) ((uint32_t)(((x) & 0x7) << 0))
236 #define EXT_MEM_WRITE_CYCLES(x) ((uint32_t)(((x) & 0x7) << 3))
237 #define EXT_MEM_TURN_CYCLES(x) ((uint32_t)(((x) & 0x7) << 6))
238 #define EXT_MEM_SIZE ((uint32_t)(1 << 16))
240 #define EXT_MEM_EDAC ((uint32_t)(1 << 24))
243 #define EXT_MEM_SIZE_FORCE ((uint32_t)(1 << 30))
245 #define EXT_MEM_EDAC_FORCE ((uint32_t)(1 << 31))
251 #define EDAC_En_1 ((uint32_t)(1 << 0))
252 #define EDAC_En_2 ((uint32_t)(1 << 1))
253 #define EDAC_WR_DIS_1 ((uint32_t)(1 << 2))
254 #define EDAC_WR_DIS_2 ((uint32_t)(1 << 3))
259 #define INTMEM_CERR_CNT(x) ((uint32_t)((x&0xFFFFFFFF) << 0))
264 #define INTMEM_FERR_CNT(x) ((uint32_t)((x&0xFFFFFFFF) << 0))
269 #define EXTMEM_CERR_CNT(x) ((uint32_t)((x&0xFFFFFFFF) << 0))
274 #define EXTMEM_FERR_CNT(x) ((uint32_t)((x&0xFFFFFFFF) << 0))
279 #define SPACEWIRE_CLK_CTRL(x) ((uint32_t)(x << 16))
286 #define NTMEM2_CERR_CNT(x) ((uint32_t)((x&0xFFFFFFFF) << 0))
291 #define INTMEM2_FERR_CNT(x) ((uint32_t)((x&0xFFFFFFFF) << 0))
312 #define PWR_CTRL_CLK(x) ((uint32_t)((x&0xFFFFFFFF) << 0))
332 #define PWR_CTRL_RST(x) ((uint32_t)((x&0xFFFFFFFF) << 0))
337 #define EXT_MEM_READ_CYCLES_2_4(x) ((uint32_t)(((x) & 0x7) << 0))
339 #define EXT_MEM_WRITE_CYCLES_2_4(x) ((uint32_t)(((x) & 0x7) << 3))
341 #define EXT_MEM_TURN_CYCLES_2_4(x) ((uint32_t)(((x) & 0x7) << 6))
343 #define EXT_MEM_SIZE_2_4 ((uint32_t)(1 << 16))
344 #define EXT_MEM_EDAC_2_4 ((uint32_t)(1 << 24))
350 #define CACHE_HIGH_ADDR(x) ((uint32_t)((x&0x7FFFFF) << 2))
358 #define CACHE_HIGH_ADDR_CS2(x) ((uint32_t)((x&0x7FFFFF) << 2))
366 #define CACHE_HIGH_ADDR_CS3(x) ((uint32_t)((x&0x7FFFFF) << 2))
374 #define CACHE_HIGH_ADDR_CS4(x) ((uint32_t)((x&0x7FFFFF) << 3))
382 #define INTMEM_SCR_RNG_ADDR(x) ((uint32_t)((x&0x1FFF) << 3))
387 #define INTMEM2_SCR_RNG_ADDR(x) ((uint32_t)((x&0x1FFF) << 3))
392 #define INTMEM_SCR_PRD_SCAN(x) ((uint32_t)((x&0xFFFFFFFF) << 0))
397 #define INTMEM2_SCR_PRD_SCAN(x) ((uint32_t)((x&0xFFFFFFFF) << 0))
402 #define INTMEM_SCR_PRD_STOP(x) ((uint32_t)((x&0xFFFFFFFF) << 0))
407 #define INTMEM2_SCR_PRD_STOP(x) ((uint32_t)((x&0xFFFFFFFF) << 0))
412 #define SCRUB_BLK1_EN ((uint32_t)((1<< 0))
413 #define SCRUB_BLK2_EN ((uint32_t)((1<< 1))
414 #define SCRUB_BLK1_READY ((uint32_t)((1<< 2))
415 #define SCRUB_BLK2_READY ((uint32_t)((1<< 2))
416 #define SCRUB_BLK1_CS_READY(x) ((uint32_t)((x&0xF) << 4))
417 #define SCRUB_BLK2_CS_READY(x) ((uint32_t)((x&0xF) << 8))
440 #define DMA_INTR_FLAGS(x) ((uint32_t)(((x) & x&0xFF) << 0))
445 #define BIT_FUNC(x) ((uint32_t)((x&0xFFFFFFFF) << 0))
450 #define INTMEM_ALIAS(x) ((uint32_t)((x&0x3) << 0))
456 #define EXTMEM_ALIAS(x) ((uint32_t)((x&0x3) << 2))
478 #define EXTMEM_CERR(x) ((uint32_t)((x&0xF) << 0))
479 #define EXTMEM_FERR(x) ((uint32_t)((x&0xF) << 3))
480 #define INTMEM_CERR(x) ((uint32_t)((x&0xF) << 6))
481 #define INTMEM_FERR(x) ((uint32_t)((x&0xF) << 9))
482 #define INTMEM_SCR_CERR(x) ((uint32_t)((x&0xF) << 12))
483 #define INTMEM_SCR_FERR(x) ((uint32_t)((x&0xF) << 15))
484 #define CACHE_CRC_ERR(x) ((uint32_t)((x&0xF) << 18))
485 
486 
490 #define CACHE_ENABLE(x) ((uint32_t)(x<< 0))
491 #define CACHE_READY(x) ((uint32_t)(x<< 1))
497 void NVIC_EnableIRQ(IRQn_T IRQn,uint32_t vec);
498 
499 
500 #define NVIC_En_IRQ(X) *((volatile unsigned int *)(0xE000E100 + (X>>5)*4)) = (1<<(X%32));
501 #define NVIC_Dis_IRQ(X) *((volatile unsigned int *)(0xE000E180 + (X>>5)*4)) = (1<<(X%32));
502 
503 
507 typedef struct
508 {
509  __RW uint32_t ISER[8];
510  uint32_t RESERVED0[24];
511  __RW uint32_t ICER[8];
512  uint32_t RESERVED1[24];
513  __RW uint32_t ISPR[8];
514  uint32_t RESERVED2[24];
515  __RW uint32_t ICPR[8];
516  uint32_t RESERVED4[88];
517  __RW uint8_t IP[240];
518 }NVIC_T;
519 
522 typedef struct
523 {
524  __RW uint32_t CTRL;
525  __RW uint32_t LOAD;
526  __RW uint32_t VAL;
527  __RO uint32_t CALIB;
528 } SYSTICK_T;
529 
532 typedef struct
533 {
534  __RO uint32_t CPUID;
535  __RW uint32_t ICSR;
536  __RW uint32_t AIRCR;
537  __RW uint32_t SCR;
538  __RO uint32_t CCR;
539  __RW uint32_t SHPR2;
540  __RW uint32_t SHPR3;
541 } SCB_T;
542 
543 
544 
562 typedef enum
563 {
565  SPI_2_CTRL_NUM = 1,
566  UART_1_CTRL_NUM = 2,
567  UART_2_CTRL_NUM = 3,
568  UART_3_CTRL_NUM = 4,
569  UART_4_CTRL_NUM = 5,
572  MKPD1_CTRL_NUM = 8,
575  MKPD4_CTRL_NUM = 11,
576  TMTX_CTRL_NUM = 12,
577  TCRX_CTRL_NUM = 13,
578  FPU_CTRL_NUM = 14,
579  RES_P1_CTRL_NUM =15,
581  RES_P3_CTRL_NUM =17,
595 void NVIC_EnableIRQ(IRQn_T IRQn,uint32_t vec);
600 void NVIC_DisableIRQ(uint32_t vec);
601 
605 #define SYST_CTRL_EN ((uint32_t)(1 << 0))
606 #define SYST_CTRL_INT_EN ((uint32_t)(1 << 1))
607 #define SYST_CTRL_CLKSRC_REF ((uint32_t)(0 << 2))
608 #define SYST_CTRL_CLKSRC_CPU ((uint32_t)(1 << 2))
609 #define SYST_CTRL_COUNTFL ((uint32_t)(1 << 16))
614 #define SYST_LOAD(x) ((uint32_t)((x) & 0xFFFFFF))
619 #define SYST_VAL(x) ((uint32_t)((x) & 0xFFFFFF))
624 #define SYST_CALIB_TENMS(x) ((uint32_t)((x) & 0xFFFFFF))
625 #define SYST_CALIB_SKEW ((uint32_t)(1 << 30))
626 #define SYST_CALIB_NOREF ((uint32_t)(1 << 31))
631 #define SCB_CPUID_IMP(x) ((uint32_t)(((x) >> 0) & 0xF))
632 #define SCB_CPUID_VAR(x) ((uint32_t)(((x) >> 4) & 0xFFF))
633 #define SCB_CPUID_CONST(x) ((uint32_t)(((x) >> 16) & 0xF))
634 #define SCB_CPUID_PRTN(x) ((uint32_t)(((x) >> 20) & 0xF))
635 #define SCB_CPUID_REV(x) ((uint32_t)(((x) >> 24) & 0xFF))
640 #define SCB_ICSR_VECTACTIVE(x) ((uint32_t)(((x) >> 0) & x1F))
641 #define SCB_ICSR_VECTPENDING(x) ((uint32_t)(((x) >> 12) & 0x1F))
642 #define SCB_ICSR_ISRPENDING ((uint32_t)(1 << 22))
643 #define SCB_ICSR_PENDSTCLR ((uint32_t)(1 << 25))
644 #define SCB_ICSR_PENDSTSET ((uint32_t)(1 << 26))
645 #define SCB_ICSR_PENDSVCLR ((uint32_t)(1 << 27))
646 #define SCB_ICSR_PENDSVSET ((uint32_t)(1 << 28))
647 #define SCB_ICSR_NMIPENDSET ((uint32_t)(1 << 31))
652 #define SCB_AIRCR_VECTKEY ((uint32_t)((0x05FA) << 16))
653 #define SCB_AIRCR_ENDIANESS ((uint32_t)(1 << 15))
654 #define SCB_AIRCR_SYSRESETREQ ((uint32_t)(1 << 2))
655 #define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)(0 << 1))
660 #define SCB_SCR_SEVONPEND ((uint32_t)(1 << 4))
661 #define SCB_SCR_SLEEPDEEP ((uint32_t)(1 << 2))
662 #define SCB_SCR_SLEEPONEXIT ((uint32_t)(1 << 1))
667 #define SCB_SHPR2_PRI_11(x) ((uint32_t)(((x) & 0x3) << 30))
672 #define SCB_SHPR3_PRI_14(x) ((uint32_t)(((x) & 0x3) << 22))
673 #define SCB_SHPR3_PRI_15(x) ((uint32_t)(((x) & 0x3) << 30))
682 #define PORT_A_ALTFUNC 0
683 #define PORT_B_ALTFUNC 1
684 #define PORT_C_ALTFUNC 2
685 #define PORT_D_ALTFUNC 3
686 #define PORT_E_ALTFUNC 4
687 #define PORT_F_ALTFUNC 5
688 #define PORT_G_ALTFUNC 6
689 #define PORT_H_ALTFUNC 7
690 #define PORT_I_ALTFUNC 8
692 #define ALTFUNC_CTRL_EXTMEM_EDAC_CERR_EN ((uint32_t)(1 << 0))
694 #define ALTFUNC_CTRL_EXTMEM_EDAC_FERR_EN ((uint32_t)(1 << 1))
696 #define ALTFUNC_CTRL_INTMEM_EDAC_CERR_EN ((uint32_t)(1 << 2))
698 #define ALTFUNC_CTRL_INTMEM_EDAC_CERR_2_EN ((uint32_t)(1 << 3))
700 #define ALTFUNC_CTRL_INTMEM_EDAC_FERR_2_EN ((uint32_t)(1 << 4))
702 #define ALTFUNC_CTRL_BITMASK ((uint32_t)(0x1F << 0))
704 #define SET_ALTFUNC(PORT, BIT, FUNC) CMN_REG->ALT_FUNCTION_CTRL[PORT] = (CMN_REG->ALT_FUNCTION_CTRL[PORT] & (~(3 << (2 * BIT)))) | (FUNC << (2 * BIT))
710 #define MKPD_CLK_CTRL_TX(x) ((uint32_t)((x) & 0xFF) << 0)
712 #define MKPD_CLK_CTRL_RX(x) ((uint32_t)((x) & 0xFF) << 8)
714 #define MKPD_CLK_SPW_CLK_EN ((uint32_t)(1 << 16))
720 void PWR_CLK_Enable(CTRL_T CTRLn);
721 
730 void PWR_RST_Disable(CTRL_T CTRLn);
731 
736 void PWR_RST_Enable(CTRL_T CTRLn);
737 
741 void SystemInit(void);
742 
743 #endif
744 
__RW uint32_t INTR_MUX_CTRL_RES_P4
Definition: system.h:97
__RW uint32_t GLOBAL_RESET
Definition: system.h:227
__RW uint32_t INTR_MUX_CTRL_TCRX
Definition: system.h:84
__RW uint32_t CACHE_CRC_ERROR
Definition: system.h:212
__RW uint32_t CACHE_HIGH_ADDR_CS2
Definition: system.h:220
__RW uint32_t INTR_MUX_CTRL_CAN1
Definition: system.h:87
__RW uint32_t INTR_MUX_CTRL_UART2
Definition: system.h:66
__RW uint32_t INTR_MUX_CTRL_MKPD2
Definition: system.h:79
Этот файл содержит структуры, макросы и функции необходимые для работы с дополнительными типами...
Definition: system.h:149
Definition: system.h:144
__RW uint32_t INTR_MUX_CTRL_GPIOI
Definition: system.h:63
void SystemInit(void)
Инициализация микросхемы
Definition: system.c:352
Структура для доступа к регистрам общего назначения
Definition: system.h:187
__RW uint32_t INTR_MUX_CTRL_GPIOD
Definition: system.h:58
#define __RW
Definition: types.h:39
__RW uint32_t INTMEM2_SCR_PRD_SCAN
Definition: system.h:209
void PWR_RST_Enable(CTRL_T CTRLn)
Ввод модуля в асинхронный сброс
Definition: system.c:309
__RW uint32_t INTR_MUX_CTRL_GPIOC
Definition: system.h:57
__RW uint32_t CACHE_HIGH_ADDR_CS4
Definition: system.h:222
Definition: system.h:146
__RW uint32_t INTMEM2_SCR_PRD_STOP
Definition: system.h:210
void NVIC_EnableIRQ(IRQn_T IRQn, uint32_t vec)
Разрешение прерывания
Definition: system.c:74
Definition: system.h:145
__RW uint32_t INTR_MUX_CTRL_RES_Q
Definition: system.h:92
__RW uint32_t INTR_MUX_CTRL_SPACEWIRE1
Definition: system.h:75
__RO uint32_t INTMEM_FERR_CNT
Definition: system.h:192
Definition: system.h:138
__RW uint32_t EXTMEM3_CTRL
Definition: system.h:202
__RW uint32_t INTMEM_SCR_RNG_ADDR
Definition: system.h:205
Definition: system.h:142
CTRL_T
Номера модулей в регистрах PWR_CLK_CTRL и PWR_RST_CTRL Расшифровка битовых полей для регистров PWR_CT...
Definition: system.h:635
__RW uint32_t RES_P_SYNC
Definition: system.h:228
__RW uint32_t INTMEM2_SCR_RNG_ADDR
Definition: system.h:208
__RW uint32_t INTR_MUX_CTRL_DMAUART3_TX
Definition: system.h:107
__RW uint32_t INTMEMS_SCR_MAIN
Definition: system.h:211
#define __RO
Definition: types.h:37
Definition: system.h:139
__RW uint32_t INTR_MUX_CTRL_DMAUART4_TX
Definition: system.h:109
__RW uint32_t INTR_MUX_CTRL_Timer3
Definition: system.h:52
__RW uint32_t INTR_MUX_CTRL_UART3
Definition: system.h:67
__RO uint32_t INTMEM2_FERR_CNT
Definition: system.h:198
__RW uint32_t EDAC_INTMEM_SCR_CERR
Definition: system.h:213
Этот файл содержит описание адресного пространства микроконтроллера 5023ВС016.
__RW uint32_t INTR_MUX_CTRL_CAN2
Definition: system.h:88
Definition: system.h:133
Definition: system.h:143
__RW uint32_t EDAC_INTMEM2_SCR_FERR
Definition: system.h:216
__RW uint32_t INTR_MUX_CTRL_MKPD1
Definition: system.h:78
__RW uint32_t EDAC_INTMEM_SCR_FERR
Definition: system.h:214
Регистр мультиплексора прерываний
Definition: system.h:47
__RW uint32_t INTMEM_SCR_PRD_STOP
Definition: system.h:207
Definition: system.h:131
__RW uint32_t INTR_MUX_CTRL_DMAUART2_RX
Definition: system.h:106
__RO uint32_t COMMON_FERR_ADDR
Definition: system.h:225
__RW uint32_t INTR_MUX_CTRL_DMASPI2_RX
Definition: system.h:102
__RW uint32_t INTMEM_SCR_PRD_SCAN
Definition: system.h:206
void PWR_CLK_Disable(CTRL_T CTRLn)
Отключение тактового сигнала от модуля
Definition: system.c:328
__RW uint32_t INTR_MUX_CTRL_UART5
Definition: system.h:69
__RW uint32_t INTR_MUX_CTRL_DMAUART3_RX
Definition: system.h:108
Definition: system.h:135
__RW uint32_t INTR_MUX_CTRL_GPIOA
Definition: system.h:55
uint32_t RESERVED
Definition: system.h:195
Definition: system.h:129
__RW uint32_t SPACEWIRE_CLK_CTRL
Definition: system.h:196
Структура для доступа к регистрам управления прерываниями
Definition: system.h:580
__RW uint32_t INTR_MUX_CTRL_SPACEWIRE2
Definition: system.h:76
__RW uint32_t INTR_MUX_CTRL_Timer4
Definition: system.h:53
Definition: system.h:130
__RW uint32_t DMA_INTR_FLAGS
Definition: system.h:217
__RW uint32_t INTR_MUX_CTRL_Watchdog
Definition: system.h:49
__RW uint32_t EDAC_CTRL
Definition: system.h:190
__RW uint32_t INTR_MUX_CTRL_RES_P2
Definition: system.h:95
__RW uint32_t INTR_MUX_CTRL_RES_P1
Definition: system.h:94
__RW uint32_t CACHE_HIGH_ADDR_CS3
Definition: system.h:221
__RW uint32_t INTR_MUX_CTRL_UART6
Definition: system.h:70
const uint32_t sys_freq
Системная частота
Definition: main.c:31
__RW uint32_t EDAC_INTMEM2_SCR_CERR
Definition: system.h:215
__RW uint32_t INTR_MUX_CTRL_UART1
Definition: system.h:65
__RW uint32_t INTR_MUX_CTRL_SPI1
Definition: system.h:72
Definition: system.h:147
__RW uint32_t INTR_MUX_CTRL_DMAUART6_RX
Definition: system.h:114
Definition: system.h:141
Структура для доступа к регистрам системного контроля
Definition: system.h:605
__RW uint32_t CACHE_HIGH_ADDR
Definition: system.h:204
__RW uint32_t PWR_CTRL_RST
Definition: system.h:200
Definition: system.h:161
void PWR_RST_Disable(CTRL_T CTRLn)
Вывод модуля из асинхронного сброса
Definition: system.c:318
__RW uint32_t EXTMEM_CTRL
Definition: system.h:189
__RW uint32_t INTR_MUX_CTRL_Timer2
Definition: system.h:51
Структура для доступа к регистрам системного таймера
Definition: system.h:595
__RW uint32_t INTR_MUX_CTRL_DMAUART5_RX
Definition: system.h:112
__RW uint32_t INTR_MUX_CTRL_GPIOE
Definition: system.h:59
__RW uint32_t INTR_MUX_CTRL_TMTX
Definition: system.h:83
__RW uint32_t EDAC_REACTION_CTRL
Definition: system.h:226
Definition: system.h:134
__RW uint32_t INTR_MUX_CTRL_Timer1
Definition: system.h:50
Definition: system.h:136
Definition: system.h:148
__RW uint32_t INTR_MUX_CTRL_DMAUART4_RX
Definition: system.h:110
void NVIC_DisableIRQ(uint32_t vec)
Запрещение прерывания
Definition: system.c:347
__RW uint32_t INTR_MUX_CTRL_GPIOG
Definition: system.h:61
__RW uint32_t INTR_MUX_CTRL_DMAUART1_RX
Definition: system.h:104
Definition: system.h:140
__RW uint32_t INTR_MUX_CTRL_DMAUART5_TX
Definition: system.h:111
__RW uint32_t INTR_MUX_CTRL_DMASPI2_TX
Definition: system.h:101
__RO uint32_t EXTMEM_FERR_CNT
Definition: system.h:194
__RW uint32_t EXTMEM4_CTRL
Definition: system.h:203
__RW uint32_t PWR_CTRL_CLK
Definition: system.h:199
__RW uint32_t INTR_MUX_CTRL_DMAUART6_TX
Definition: system.h:113
__RW uint32_t INTR_MUX_CTRL_SPI2
Definition: system.h:73
__RW uint32_t INTR_MUX_CTRL_I2C
Definition: system.h:85
__RW uint32_t INTR_MUX_CTRL_DMASPI1_RX
Definition: system.h:100
__RW uint32_t INTR_MUX_CTRL_MKPD3
Definition: system.h:80
__RW uint32_t INTR_MUX_CTRL_DMAUART2_TX
Definition: system.h:105
IRQn_T
Номера прерываний в регистрах NVIC.
Definition: system.h:126
__RW uint32_t INTR_MUX_CTRL_EDAC
Definition: system.h:90
const uint32_t spw_freq
Definition: system.h:132
__RW uint32_t INTR_MUX_CTRL_MKPD4
Definition: system.h:81
__RW uint32_t INTR_MUX_CTRL_UART4
Definition: system.h:68
__RW uint32_t INTR_MUX_CTRL_RES_P3
Definition: system.h:96
__RW uint32_t INTR_MUX_CTRL_GPIOF
Definition: system.h:60
__RO uint32_t EXTMEM_CERR_CNT
Definition: system.h:193
__RW uint32_t EXTMEM2_CTRL
Definition: system.h:201
__RW uint32_t INTR_MUX_CTRL_GPIOH
Definition: system.h:62
__RW uint32_t ALIAS_CTRL
Definition: system.h:223
__RW uint32_t INTR_MUX_CTRL_DMASPI1_TX
Definition: system.h:99
__RW uint32_t INTR_MUX_CTRL_DMAUART1_TX
Definition: system.h:103
__RO uint32_t SCRUBBER_FERR_ADDR
Definition: system.h:224
__RW uint32_t INTR_MUX_CTRL_GPIOB
Definition: system.h:56
__RO uint32_t INTMEM2_CERR_CNT
Definition: system.h:197
__RO uint32_t INTMEM_CERR_CNT
Definition: system.h:191
Definition: system.h:137
__RW uint32_t CACHE_MAIN
Definition: system.h:229