40 #define CLK_INIT_PAUSE for(int i=0; i<100000; i++) 41 #define CLK_FPU_PAUSE for(int i=0; i<100; i++) 42 #define CLK_UART_PAUSE for(int i=0; i<10000; i++) 64 __RW uint32_t RESERVED1[7];
71 __RW uint32_t RESERVED2[2];
74 __RW uint32_t RESERVED3[2];
77 __RW uint32_t RESERVED4[2];
82 __RW uint32_t RESERVED5[4];
86 __RW uint32_t RESERVED6[1];
89 __RW uint32_t RESERVED7[2];
91 __RW uint32_t RESERVED8[3];
93 __RW uint32_t RESERVED9[3];
98 __RW uint32_t RESERVED10[28];
120 #define INTR_SRC_ENABLE ((uint32_t)(1<<31)) 121 #define NUM_INTR_VECTOR(x) ((uint32_t)((x&0x1F)<<0)) 218 __RW uint32_t ALT_FUNCTION_CTRL[9];
235 #define EXT_MEM_READ_CYCLES(x) ((uint32_t)(((x) & 0x7) << 0)) 236 #define EXT_MEM_WRITE_CYCLES(x) ((uint32_t)(((x) & 0x7) << 3)) 237 #define EXT_MEM_TURN_CYCLES(x) ((uint32_t)(((x) & 0x7) << 6)) 238 #define EXT_MEM_SIZE ((uint32_t)(1 << 16)) 240 #define EXT_MEM_EDAC ((uint32_t)(1 << 24)) 243 #define EXT_MEM_SIZE_FORCE ((uint32_t)(1 << 30)) 245 #define EXT_MEM_EDAC_FORCE ((uint32_t)(1 << 31)) 251 #define EDAC_En_1 ((uint32_t)(1 << 0)) 252 #define EDAC_En_2 ((uint32_t)(1 << 1)) 253 #define EDAC_WR_DIS_1 ((uint32_t)(1 << 2)) 254 #define EDAC_WR_DIS_2 ((uint32_t)(1 << 3)) 259 #define INTMEM_CERR_CNT(x) ((uint32_t)((x&0xFFFFFFFF) << 0)) 264 #define INTMEM_FERR_CNT(x) ((uint32_t)((x&0xFFFFFFFF) << 0)) 269 #define EXTMEM_CERR_CNT(x) ((uint32_t)((x&0xFFFFFFFF) << 0)) 274 #define EXTMEM_FERR_CNT(x) ((uint32_t)((x&0xFFFFFFFF) << 0)) 279 #define SPACEWIRE_CLK_CTRL(x) ((uint32_t)(x << 16)) 286 #define NTMEM2_CERR_CNT(x) ((uint32_t)((x&0xFFFFFFFF) << 0)) 291 #define INTMEM2_FERR_CNT(x) ((uint32_t)((x&0xFFFFFFFF) << 0)) 312 #define PWR_CTRL_CLK(x) ((uint32_t)((x&0xFFFFFFFF) << 0)) 332 #define PWR_CTRL_RST(x) ((uint32_t)((x&0xFFFFFFFF) << 0)) 337 #define EXT_MEM_READ_CYCLES_2_4(x) ((uint32_t)(((x) & 0x7) << 0)) 339 #define EXT_MEM_WRITE_CYCLES_2_4(x) ((uint32_t)(((x) & 0x7) << 3)) 341 #define EXT_MEM_TURN_CYCLES_2_4(x) ((uint32_t)(((x) & 0x7) << 6)) 343 #define EXT_MEM_SIZE_2_4 ((uint32_t)(1 << 16)) 344 #define EXT_MEM_EDAC_2_4 ((uint32_t)(1 << 24)) 350 #define CACHE_HIGH_ADDR(x) ((uint32_t)((x&0x7FFFFF) << 2)) 358 #define CACHE_HIGH_ADDR_CS2(x) ((uint32_t)((x&0x7FFFFF) << 2)) 366 #define CACHE_HIGH_ADDR_CS3(x) ((uint32_t)((x&0x7FFFFF) << 2)) 374 #define CACHE_HIGH_ADDR_CS4(x) ((uint32_t)((x&0x7FFFFF) << 3)) 382 #define INTMEM_SCR_RNG_ADDR(x) ((uint32_t)((x&0x1FFF) << 3)) 387 #define INTMEM2_SCR_RNG_ADDR(x) ((uint32_t)((x&0x1FFF) << 3)) 392 #define INTMEM_SCR_PRD_SCAN(x) ((uint32_t)((x&0xFFFFFFFF) << 0)) 397 #define INTMEM2_SCR_PRD_SCAN(x) ((uint32_t)((x&0xFFFFFFFF) << 0)) 402 #define INTMEM_SCR_PRD_STOP(x) ((uint32_t)((x&0xFFFFFFFF) << 0)) 407 #define INTMEM2_SCR_PRD_STOP(x) ((uint32_t)((x&0xFFFFFFFF) << 0)) 412 #define SCRUB_BLK1_EN ((uint32_t)((1<< 0)) 413 #define SCRUB_BLK2_EN ((uint32_t)((1<< 1)) 414 #define SCRUB_BLK1_READY ((uint32_t)((1<< 2)) 415 #define SCRUB_BLK2_READY ((uint32_t)((1<< 2)) 416 #define SCRUB_BLK1_CS_READY(x) ((uint32_t)((x&0xF) << 4)) 417 #define SCRUB_BLK2_CS_READY(x) ((uint32_t)((x&0xF) << 8)) 440 #define DMA_INTR_FLAGS(x) ((uint32_t)(((x) & x&0xFF) << 0)) 445 #define BIT_FUNC(x) ((uint32_t)((x&0xFFFFFFFF) << 0)) 450 #define INTMEM_ALIAS(x) ((uint32_t)((x&0x3) << 0)) 456 #define EXTMEM_ALIAS(x) ((uint32_t)((x&0x3) << 2)) 478 #define EXTMEM_CERR(x) ((uint32_t)((x&0xF) << 0)) 479 #define EXTMEM_FERR(x) ((uint32_t)((x&0xF) << 3)) 480 #define INTMEM_CERR(x) ((uint32_t)((x&0xF) << 6)) 481 #define INTMEM_FERR(x) ((uint32_t)((x&0xF) << 9)) 482 #define INTMEM_SCR_CERR(x) ((uint32_t)((x&0xF) << 12)) 483 #define INTMEM_SCR_FERR(x) ((uint32_t)((x&0xF) << 15)) 484 #define CACHE_CRC_ERR(x) ((uint32_t)((x&0xF) << 18)) 490 #define CACHE_ENABLE(x) ((uint32_t)(x<< 0)) 491 #define CACHE_READY(x) ((uint32_t)(x<< 1)) 497 void NVIC_EnableIRQ(IRQn_T IRQn,uint32_t vec); 500 #define NVIC_En_IRQ(X) *((volatile unsigned int *)(0xE000E100 + (X>>5)*4)) = (1<<(X%32)); 501 #define NVIC_Dis_IRQ(X) *((volatile unsigned int *)(0xE000E180 + (X>>5)*4)) = (1<<(X%32)); 509 __RW uint32_t ISER[8];
510 uint32_t RESERVED0[24];
512 uint32_t RESERVED1[24];
513 __RW uint32_t ISPR[8];
514 uint32_t RESERVED2[24];
515 __RW uint32_t ICPR[8];
516 uint32_t RESERVED4[88];
517 __RW uint8_t IP[240];
605 #define SYST_CTRL_EN ((uint32_t)(1 << 0)) 606 #define SYST_CTRL_INT_EN ((uint32_t)(1 << 1)) 607 #define SYST_CTRL_CLKSRC_REF ((uint32_t)(0 << 2)) 608 #define SYST_CTRL_CLKSRC_CPU ((uint32_t)(1 << 2)) 609 #define SYST_CTRL_COUNTFL ((uint32_t)(1 << 16)) 614 #define SYST_LOAD(x) ((uint32_t)((x) & 0xFFFFFF)) 619 #define SYST_VAL(x) ((uint32_t)((x) & 0xFFFFFF)) 624 #define SYST_CALIB_TENMS(x) ((uint32_t)((x) & 0xFFFFFF)) 625 #define SYST_CALIB_SKEW ((uint32_t)(1 << 30)) 626 #define SYST_CALIB_NOREF ((uint32_t)(1 << 31)) 631 #define SCB_CPUID_IMP(x) ((uint32_t)(((x) >> 0) & 0xF)) 632 #define SCB_CPUID_VAR(x) ((uint32_t)(((x) >> 4) & 0xFFF)) 633 #define SCB_CPUID_CONST(x) ((uint32_t)(((x) >> 16) & 0xF)) 634 #define SCB_CPUID_PRTN(x) ((uint32_t)(((x) >> 20) & 0xF)) 635 #define SCB_CPUID_REV(x) ((uint32_t)(((x) >> 24) & 0xFF)) 640 #define SCB_ICSR_VECTACTIVE(x) ((uint32_t)(((x) >> 0) & x1F)) 641 #define SCB_ICSR_VECTPENDING(x) ((uint32_t)(((x) >> 12) & 0x1F)) 642 #define SCB_ICSR_ISRPENDING ((uint32_t)(1 << 22)) 643 #define SCB_ICSR_PENDSTCLR ((uint32_t)(1 << 25)) 644 #define SCB_ICSR_PENDSTSET ((uint32_t)(1 << 26)) 645 #define SCB_ICSR_PENDSVCLR ((uint32_t)(1 << 27)) 646 #define SCB_ICSR_PENDSVSET ((uint32_t)(1 << 28)) 647 #define SCB_ICSR_NMIPENDSET ((uint32_t)(1 << 31)) 652 #define SCB_AIRCR_VECTKEY ((uint32_t)((0x05FA) << 16)) 653 #define SCB_AIRCR_ENDIANESS ((uint32_t)(1 << 15)) 654 #define SCB_AIRCR_SYSRESETREQ ((uint32_t)(1 << 2)) 655 #define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)(0 << 1)) 660 #define SCB_SCR_SEVONPEND ((uint32_t)(1 << 4)) 661 #define SCB_SCR_SLEEPDEEP ((uint32_t)(1 << 2)) 662 #define SCB_SCR_SLEEPONEXIT ((uint32_t)(1 << 1)) 667 #define SCB_SHPR2_PRI_11(x) ((uint32_t)(((x) & 0x3) << 30)) 672 #define SCB_SHPR3_PRI_14(x) ((uint32_t)(((x) & 0x3) << 22)) 673 #define SCB_SHPR3_PRI_15(x) ((uint32_t)(((x) & 0x3) << 30)) 682 #define PORT_A_ALTFUNC 0 683 #define PORT_B_ALTFUNC 1 684 #define PORT_C_ALTFUNC 2 685 #define PORT_D_ALTFUNC 3 686 #define PORT_E_ALTFUNC 4 687 #define PORT_F_ALTFUNC 5 688 #define PORT_G_ALTFUNC 6 689 #define PORT_H_ALTFUNC 7 690 #define PORT_I_ALTFUNC 8 692 #define ALTFUNC_CTRL_EXTMEM_EDAC_CERR_EN ((uint32_t)(1 << 0)) 694 #define ALTFUNC_CTRL_EXTMEM_EDAC_FERR_EN ((uint32_t)(1 << 1)) 696 #define ALTFUNC_CTRL_INTMEM_EDAC_CERR_EN ((uint32_t)(1 << 2)) 698 #define ALTFUNC_CTRL_INTMEM_EDAC_CERR_2_EN ((uint32_t)(1 << 3)) 700 #define ALTFUNC_CTRL_INTMEM_EDAC_FERR_2_EN ((uint32_t)(1 << 4)) 702 #define ALTFUNC_CTRL_BITMASK ((uint32_t)(0x1F << 0)) 704 #define SET_ALTFUNC(PORT, BIT, FUNC) CMN_REG->ALT_FUNCTION_CTRL[PORT] = (CMN_REG->ALT_FUNCTION_CTRL[PORT] & (~(3 << (2 * BIT)))) | (FUNC << (2 * BIT)) 710 #define MKPD_CLK_CTRL_TX(x) ((uint32_t)((x) & 0xFF) << 0) 712 #define MKPD_CLK_CTRL_RX(x) ((uint32_t)((x) & 0xFF) << 8) 714 #define MKPD_CLK_SPW_CLK_EN ((uint32_t)(1 << 16)) 720 void PWR_CLK_Enable(CTRL_T CTRLn); __RW uint32_t INTR_MUX_CTRL_RES_P4
__RW uint32_t GLOBAL_RESET
__RW uint32_t INTR_MUX_CTRL_TCRX
__RW uint32_t CACHE_CRC_ERROR
__RW uint32_t CACHE_HIGH_ADDR_CS2
__RW uint32_t INTR_MUX_CTRL_CAN1
__RW uint32_t INTR_MUX_CTRL_UART2
__RW uint32_t INTR_MUX_CTRL_MKPD2
Этот файл содержит структуры, макросы и функции необходимые для работы с дополнительными типами...
__RW uint32_t INTR_MUX_CTRL_GPIOI
void SystemInit(void)
Инициализация микросхемы
Структура для доступа к регистрам общего назначения
__RW uint32_t INTR_MUX_CTRL_GPIOD
__RW uint32_t INTMEM2_SCR_PRD_SCAN
void PWR_RST_Enable(CTRL_T CTRLn)
Ввод модуля в асинхронный сброс
__RW uint32_t INTR_MUX_CTRL_GPIOC
__RW uint32_t CACHE_HIGH_ADDR_CS4
__RW uint32_t INTMEM2_SCR_PRD_STOP
void NVIC_EnableIRQ(IRQn_T IRQn, uint32_t vec)
Разрешение прерывания
__RW uint32_t INTR_MUX_CTRL_RES_Q
__RW uint32_t INTR_MUX_CTRL_SPACEWIRE1
__RO uint32_t INTMEM_FERR_CNT
__RW uint32_t EXTMEM3_CTRL
__RW uint32_t INTMEM_SCR_RNG_ADDR
CTRL_T
Номера модулей в регистрах PWR_CLK_CTRL и PWR_RST_CTRL Расшифровка битовых полей для регистров PWR_CT...
__RW uint32_t INTMEM2_SCR_RNG_ADDR
__RW uint32_t INTR_MUX_CTRL_DMAUART3_TX
__RW uint32_t INTMEMS_SCR_MAIN
__RW uint32_t INTR_MUX_CTRL_DMAUART4_TX
__RW uint32_t INTR_MUX_CTRL_Timer3
__RW uint32_t INTR_MUX_CTRL_UART3
__RO uint32_t INTMEM2_FERR_CNT
__RW uint32_t EDAC_INTMEM_SCR_CERR
Этот файл содержит описание адресного пространства микроконтроллера 5023ВС016.
__RW uint32_t INTR_MUX_CTRL_CAN2
__RW uint32_t EDAC_INTMEM2_SCR_FERR
__RW uint32_t INTR_MUX_CTRL_MKPD1
__RW uint32_t EDAC_INTMEM_SCR_FERR
Регистр мультиплексора прерываний
__RW uint32_t INTMEM_SCR_PRD_STOP
__RW uint32_t INTR_MUX_CTRL_DMAUART2_RX
__RO uint32_t COMMON_FERR_ADDR
__RW uint32_t INTR_MUX_CTRL_DMASPI2_RX
__RW uint32_t INTMEM_SCR_PRD_SCAN
void PWR_CLK_Disable(CTRL_T CTRLn)
Отключение тактового сигнала от модуля
__RW uint32_t INTR_MUX_CTRL_UART5
__RW uint32_t INTR_MUX_CTRL_DMAUART3_RX
__RW uint32_t INTR_MUX_CTRL_GPIOA
__RW uint32_t SPACEWIRE_CLK_CTRL
Структура для доступа к регистрам управления прерываниями
__RW uint32_t INTR_MUX_CTRL_SPACEWIRE2
__RW uint32_t INTR_MUX_CTRL_Timer4
__RW uint32_t DMA_INTR_FLAGS
__RW uint32_t INTR_MUX_CTRL_Watchdog
__RW uint32_t INTR_MUX_CTRL_RES_P2
__RW uint32_t INTR_MUX_CTRL_RES_P1
__RW uint32_t CACHE_HIGH_ADDR_CS3
__RW uint32_t INTR_MUX_CTRL_UART6
const uint32_t sys_freq
Системная частота
__RW uint32_t EDAC_INTMEM2_SCR_CERR
__RW uint32_t INTR_MUX_CTRL_UART1
__RW uint32_t INTR_MUX_CTRL_SPI1
__RW uint32_t INTR_MUX_CTRL_DMAUART6_RX
Структура для доступа к регистрам системного контроля
__RW uint32_t CACHE_HIGH_ADDR
__RW uint32_t PWR_CTRL_RST
void PWR_RST_Disable(CTRL_T CTRLn)
Вывод модуля из асинхронного сброса
__RW uint32_t EXTMEM_CTRL
__RW uint32_t INTR_MUX_CTRL_Timer2
Структура для доступа к регистрам системного таймера
__RW uint32_t INTR_MUX_CTRL_DMAUART5_RX
__RW uint32_t INTR_MUX_CTRL_GPIOE
__RW uint32_t INTR_MUX_CTRL_TMTX
__RW uint32_t EDAC_REACTION_CTRL
__RW uint32_t INTR_MUX_CTRL_Timer1
__RW uint32_t INTR_MUX_CTRL_DMAUART4_RX
void NVIC_DisableIRQ(uint32_t vec)
Запрещение прерывания
__RW uint32_t INTR_MUX_CTRL_GPIOG
__RW uint32_t INTR_MUX_CTRL_DMAUART1_RX
__RW uint32_t INTR_MUX_CTRL_DMAUART5_TX
__RW uint32_t INTR_MUX_CTRL_DMASPI2_TX
__RO uint32_t EXTMEM_FERR_CNT
__RW uint32_t EXTMEM4_CTRL
__RW uint32_t PWR_CTRL_CLK
__RW uint32_t INTR_MUX_CTRL_DMAUART6_TX
__RW uint32_t INTR_MUX_CTRL_SPI2
__RW uint32_t INTR_MUX_CTRL_I2C
__RW uint32_t INTR_MUX_CTRL_DMASPI1_RX
__RW uint32_t INTR_MUX_CTRL_MKPD3
__RW uint32_t INTR_MUX_CTRL_DMAUART2_TX
IRQn_T
Номера прерываний в регистрах NVIC.
__RW uint32_t INTR_MUX_CTRL_EDAC
__RW uint32_t INTR_MUX_CTRL_MKPD4
__RW uint32_t INTR_MUX_CTRL_UART4
__RW uint32_t INTR_MUX_CTRL_RES_P3
__RW uint32_t INTR_MUX_CTRL_GPIOF
__RO uint32_t EXTMEM_CERR_CNT
__RW uint32_t EXTMEM2_CTRL
__RW uint32_t INTR_MUX_CTRL_GPIOH
__RW uint32_t INTR_MUX_CTRL_DMASPI1_TX
__RW uint32_t INTR_MUX_CTRL_DMAUART1_TX
__RO uint32_t SCRUBBER_FERR_ADDR
__RW uint32_t INTR_MUX_CTRL_GPIOB
__RO uint32_t INTMEM2_CERR_CNT
__RO uint32_t INTMEM_CERR_CNT